1. Field of the Invention
The present invention generally relates to an electronic device, a method of manufacturing the electronic device, a contact hole of the electronic device, a method of forming the contact hole, a display element including the electronic device, a display device including the display element, a semiconductor arithmetic element including the electronic device, and a computer including the semiconductor arithmetic element, in which the electronic device is applicable to various electronic devices using multilayered wiring and electrodes.
2. Description of the Related Art
In recent years and continuing, the demand for fabricating electron elements with multilayer configurations and providing fine wiring technology is growing as electron elements, such as semiconductor operation elements, become highly integrated, as seen with VLSI and ULSI, for example.
FIG. 12 shows an example of a semiconductor arithmetic circuit. In FIG. 12, p-ch and n-ch exhibit a transistor using a hole transfer material and a transistor using an electron transfer material, respectively. Although the exemplary circuit shown in FIG. 12 is a NOT arithmetic circuit, multiple transistors 400 may be integrated/connected via interlayer insulating films 501, 502, 503, 504 so as to form other arithmetic circuits such as OR, NAND, NOR, and XOR. That is, as shown in FIG. 13A, fine-sized wiring electrodes 510 are formed in contact holes 511 penetrating the interlayer insulation films 502, 503, 504 in a vertical direction in FIG. 13A, and fine wiring electrodes 515 are formed extending in a horizontal direction in FIG. 13A on the interlayer insulation films 501-504 (at each interface between the interlayer insulation layers 501 and 502, the interlayer insulation layers 502 and 503, and interlayer insulation layers 503 and 504). By connecting the wiring electrodes 511 and 515 to corresponding source electrodes 403 and drain electrodes 404 shown in FIG. 13B, a highly integrated semiconductor arithmetic circuit is obtained. In the transistor 400 shown in FIG. 13B, reference numeral 401 represents a gate electrode, reference numeral 402 represents a gate insulation film, and reference numeral 405 represents a semiconductor.
In a display element 610 included in a display device 600 (e.g. reflection liquid crystal device) as shown in FIG. 14, an electron device 420, which is an active element (e.g. TFT (Thin Film Transistor), is positioned on a non-displaying side of the display device 600, and a pixel electrode 602 is formed on the interlayer insulation film 505. By applying voltage between the pixel electrode 602 and an electrode (not shown) of a transparent conductive film 603, the display element 610 displays an image(s). In order to display high definition images, the pixel electrode 602 is to be finely formed on the interlayer insulation layer 505, and the electrodes are to be connected by a contact hole 512. Furthermore, in FIG. 14, reference numeral 430 represents a first substrate, reference numeral 440 represents an electron device array having multiple electron devices 420 arranged in a prescribed array, and reference numeral 601 represents a second substrate. Furthermore, in the electron device (TFT) 420, reference numeral 411 represents a gate electrode, reference numeral 412 represents a gate insulation film, reference numeral 413 represents a source electrode, reference numeral 414 represents a drain electrode, and reference numeral 415 represents a semiconductor.
In FIG. 14, the reference numerals indicated with parenthesis (i.e. display device 60, display element 61, contact hole 62, and pixel electrode 63) are used for distinguishing an embodiment of the present invention from related art cases (described below).
It is also to be noted that the interlayer insulation films 501-505 are not only deposited/formed on an electrode (electrode material), but may also be deposited/formed on a semiconductor layer (semiconductor material) in a case where a transistor is provided as shown in FIGS. 13 and 14.
FIG. 19 is a schematic diagram showing a portion of a display device 700 for describing the forming/positioning of contact holes. In a display element 710 included in the display device 700 shown in FIG. 19, an electron device 720, which is an active element (e.g. TFT), is positioned on a non-displaying side of the display device 700, and a pixel electrode 702 (first conductive material layer) is formed on the interlayer insulation film 705. By applying voltage between the pixel electrode 702 and a transparent electrode 703, the display element 710 displays an image(s). In order to display high definition images, the pixel electrode 702 is to be finely formed on the interlayer insulation layer 705, and the pixel electrode 702 and another electrode 704 (i.e. first conductive material layer and second conductive material layer) are to be connected by a contact hole 712. In FIG. 19, reference numeral 701 represents a substrate for forming, for example, an electron element 720 thereon, reference numeral 704 represents a second conductive material layer, and reference numeral 706 (i.e. the portion illustrated with broken lines) represents a retention volume. It is to be noted that the electron element 720 has a substantially similar configuration as that of the electron element 420 (TFT) shown in FIG. 13.
As a typical method for forming fine electrodes, there is a photolithography process “A” including the steps of (1)-(7) as described below.    (1) Apply photo-resist on a substrate having a thin film layer (Step of applying resist coating).    (2) Remove solvent by heating (Step of pre-baking).    (3) Irradiate ultraviolet light with use of a hard mask lithographed by a laser beam or an electron beam in accordance with prescribed pattern data (Step of exposing)    (4) Remove resist of exposed portion by using an alkali solution (Step of developing)    (5) Cure resist of unexposed portion (patterned portion) by heating (Step of post-baking)    (6) Remove a portion of the thin film layer having no resist by steeping into an etching liquid or exposing to an etching gas (Step of etching)    (7) Remove resist by using an alkali solution or an oxygen radical (Step of removing resist)
This typical method, however, requires many steps, and results in an increase of manufacturing cost.
In order to resolve this problem, a related art case discloses a method including the steps of applying organo-cycloxane onto a plane on which an electrode is formed (electrode formation plane), performing hydrophilization on a portion where the electrode is disposed by using UV exposing process, and applying a conductive ink (e.g. ultra fine particles of colloidal gold liquid or PEDOT solution) by using an inkjet method. Accordingly, in a case where the electrode formation plane is situated on an interlayer insulation film, fine electrode patterns can be formed by performing this method that is easier than the above-described photolithography process “A”.
Another related art case discloses a method for forming contact holes which is also easier than the above-described photolithography process “A”. This related case is described below with reference to FIGS. 15A-15C.
FIGS. 15A-15C show a first wiring layer 310, an interlayer insulation layer 311, a photosensitive silazane layer 312, and light beams 313. The first wiring layer 310 includes a wiring 310a for mutually connecting various functional blocks of a semiconductor device, and an interlayer insulation film 310b for conducting insulation among wirings, and a protection film 310c for preventing wiring material of the wiring 310a from diffusing to the interlayer insulation layer 311.
The interlayer insulation layer 311 is a layer for conducting insulation among wirings. The photosensitive silazane layer 312 includes a film formed of a photosensitive silazane. The photosensitive silazane includes an MSZ (Methylsilazane) having a positive photosensitivity by adding a photo-oxide generating material and a sensitizing agent thereto. The photosensitive silazane layer 312 is subjected to a process of irradiation electron beams or ultraviolet beams for generating photo-oxide (H+) therein, cutting-off an Si—N bond in the MSZ, and absorbing H2O. Then, the photosensitive silazane layer 312 is subjected to a process of developing with a TMAH (Tetra-Methyl-Ammonium-Hydroxide) solution, so as to etch the exposed portion of the photosensitive silazane layer 312. Then, the photosensitive silazane layer 312 is subjected to a heating process in which the photosensitive silazane layer 322 is cured in an N2 ambient atmosphere of approximately 400° C. Thereby, the MSZ of the photosensitive silazane layer transforms into MSQ (Methyl silsesquiaxane) having no photodecomposition property. Accordingly, the photosensitive silazane layer 312 can serve as an etch-stop layer.
The light beams 313 shown in FIG. 15 irradiated to the photosensitive silazane layer 312 may be electron beams or ultraviolet beams. Although not shown in FIGS. 15A-15C, the first wiring layer 310 is formed as a wiring for connecting with, for example, a prescribed MOS transistor formed on a silicon substrate.
More specifically, the interlayer insulation layer 311 is, first, formed on an upper surface of the first wiring layer 310 as shown in FIG. 15A. Since the interlayer insulation layer 311 serves as an insulation layer to which contact holes or wiring grooves are formed in a subsequent process, the thickness of the interlayer insulation layer 311 is same as the depth of the contact holes or no less than the depth of the wiring grooves. Then, the photosensitive silazane layer 312 is formed on an upper surface of the interlayer insulation layer 311.
Next, as shown in FIG. 15B, the light beams 313 are irradiated to the photosensitive silazane layer 312. In this process, the light beams 313 are irradiated to the photosensitive silazane layer 312 via a mask having a pattern of the contact holes or the wiring grooves that are to be formed in the interlayer insulation layer 311. Then, the portion of the photosensitive silazane layer 312 exposed by the irradiation is subjected to a developing process using a TMAH solution, so that the exposed portion can be removed to form a prescribed pattern. Then, by performing a heating process on the photosensitive silazane layer 312 in an N2 ambient atmosphere of 400° C., the MSZ of the photosensitive silazane layer 312 is transformed to MSQ. Thereby, the photosensitive silazane layer 312 can be an etch-stop layer.
Next, as shown in FIG. 15C, the contact holes or the wiring grooves are formed by etching the interlayer insulation layer 311 and further etching the protection film 310c of the first wiring layer 310.
An exemplary process of forming the contact holes, the wiring grooves, or the wirings by using a CMP (Chemical Mechanical Polishing) method is described with reference to FIGS. 16A-16C. In FIGS. 16A-16C, reference numeral 300 represents a semiconductor substrate serving as the first wiring substrate 310 including the wiring 310a, and reference numeral 315 represents a contact hole or a wiring groove. It is to be noted that the protection film 310c is omitted for the sake of convenience. With reference to FIGS. 16A-16C, first, a barrier metal is applied for preventing metal from diffusing into a semiconductor substrate 300. Then, a copper material, for example, is filled into a contact hole (wiring groove) 315, so as to form an upper electrode 320. Then, the CMP method is performed for polishing away excess copper material. Thereby, the contact hole 315, the upper electrode 320, and other wirings can be formed. By repeating this process for a given number of times, multiple layers of wiring can be formed, to thereby obtain a semiconductor device having a multilayer wiring structure.
Meanwhile, in other related art cases, an organic material is proposed to be used as a semiconductor material owing to its manufacturing advantages, such as low manufacture cost and large-area applicability as well as its possibility of realizing functions not achieved with inorganic materials. For example, as shown in Japanese Laid-Open Patent Application No. 7-86600, a field-effect transistor using an organic material having a carrier mobility that changes in correspondence with outside physical stimulas (e.g. light, heat). In another related art case, Japanese Laid-Open Patent Application No. 2003-318196 also proposes a field-effect transistor using an organic semiconductor material.
In another related art case, SiO2 is used as the material of the interlayer insulation film (interlayer insulation film), such as in Japanese Laid-Open Patent Application No. 5-36627.
In another related art case, a method of forming via holes (contact holes)/interlayer insulation films by using a photolithography process is disclosed in Japanese Laid-Open Patent Application No. 2001-168191, for example. This method is employed in manufacturing semiconductor devices and is a type of dual damascene method applied to semiconductor products. The main processes of this method are described below with reference to FIG. 20.    (1) Forming a first conductive material layer 201 on a substrate 202    (2) Forming a first organic insulation material layer 203 on the first conductive material layer 201 and the substrate 202    (3) Forming a first SiO2 layer 204 on the first organic insulation material layer 203    (4) Forming a first photosensitive material layer 205 on the first SiO2 layer 204    (5) Forming a pattern (i.e. patterning) of a contact hole by irradiating UV via a first exposure mask 206    (6) Etching the first photosensitive material layer 205    (7) Etching the SiO2 layer 204    (8) Cleaning/Drying    (9) Depositing/Forming a second organic insulation material layer 203′    (10) Forming a second SiO2 layer 204′ on the second organic insulation material layer 203′    (11) Forming a pattern (i.e. patterning) of a second conductive material layer 207 by irradiating UV via a second exposure mask 206′    (12) Etching the second photosensitive material layer 205′    (13) Etching the second SiO2 layer 204′    (14) Cleaning/Drying    (15) Removing thin film of the second organic insulation material layer 203′ by dry-etching    (16) Forming the second conductive material layer 207    (17) CMP
In another related art case, a method of forming a pattern on an insulation material by utilizing the difference of wettability is disclosed in Japanese Laid-Open Patent Application No. 2004-193197. In the method, an interlayer insulation film is formed by patterning an insulation material by changing the adhesion of the substrate with use of UV.
However, the related art case shown in Japanese Laid-Open Patent Application No. 2002-261048 requires the steps of applying a coating of insulation material on a substrate, applying a coating of organo-siloxane on the substrate, and exposing the substrate, since organo-siloxane itself does not have an insulating property. Accordingly, in a case of fabricating a multilayer configuration, an increase of steps for forming a single layer causes an increase of steps for the entire process of fabricating the multilayer configuration.
In the related art case shown in Japanese Laid-Open Patent Application No. 2003-7818 (Method of forming upper electrode by using Chemical Mechanical Polishing (CMP) as shown in FIGS. 15 and 16), it is difficult to provide a flat shape for the upper electrode 320 owing that the vicinity of the center portion of the upper electrode 320 is susceptible to being formed into a U-shape or into an inclined shape (See FIGS. 17 and 18). It is desired that the upper electrode 320 is formed having a shape as shown in FIG. 16C (shape resulting from the chemical mechanical polishing process). Therefore, it is difficult to attain satisfactory and reliable electric connection of electrodes.
In the related art case shown in Japanese Laid-Open Patent Application No. 2003-7818, although the disclosed method may be a simple method for forming the contact hole 315, the method still requires the processes of etching the interlayer insulation layer 311 and etching the protection film 310c of the first wiring layer 310. These required processes result in increase of manufacturing cost. Furthermore, since the method requires heating under a high temperature of 400° C., the materials to be used for the substrate, for example, is limited. These disadvantages are also found in the related art case shown in Japanese Laid-Open Patent Application No. 2003-318196.
In the related art case shown in Japanese Laid-Open Patent Application No. 7-86600, the organic semiconductor material layer may be damaged in a case where an interlayer insulation film is deposited by using an organic solution having little polarity (e.g. toluene, THF, xylene).
In the related art case shown in Japanese Laid-Open Patent Application No. 5-36627, although SiO2 is a reliable material for the interlayer insulation film material (owing to its high dielectric voltage), the use of SiO2 as the interlayer insulation film material increases manufacture cost since a vacuum deposition process (e.g. sputtering) is necessary for depositing/forming such interlayer insulation film.
This disadvantage is also found in a case of using materials such as Si3N4 and SiON. Accordingly, a material which has high dielectric voltage and which can be applied by a coating process (e.g. sputtering) is desired. Furthermore, the parasitic capacitance of the interlayer insulation film, which causes wiring delay, is required to be reduced. Since such wiring delay causes a decrease in operational frequency of semiconductor arithmetic elements (e.g. LSI), a material having a dielectric constant less than that of SiO2 (less than ε=3.9) is desired.
In the related art case shown in Japanese Laid-Open Patent Application No. 2001-168191, although fine patterning results can be achieved by forming the contact hole/interlayer insulation film with use of the photolithography process, such method requires many processes as shown in FIG. 20 and results in the increase of manufacture cost. The CMP process in this method (process (17) in FIG. 20) is the same as the CMP process shown in FIGS. 16(a)-(c). Accordingly, as described above, it is difficult to provide a flat shape for the upper electrode 320 owing that the vicinity of the center portion of the upper electrode 320 is susceptible to being formed into a U-shape or into an inclined shape (See FIGS. 17 and 18). Therefore, it is difficult to attain satisfactory and reliable electric connection of electrodes.
In the related art case shown in Japanese Laid-Open Patent Application No. 2004-193197, the method for patterning the insulation material also requires many complicated processes since it also uses the photolithography process for forming electrodes on the insulation film.